This invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes. More specifically, the present invention relates to techniques for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer stack.
The measurement of overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.
Although this conventional overlay design has worked well, there are continuing efforts to provide improved techniques for determining or predicting overlay in device structures.